Silicon photonics is rapidly gaining importance as a generic technology platform for a wide range of applications in telecommunications, data communications, interconnect and sensing. It allows implementing photonic functions through the use of CMOS (Complementary Metal Oxide Semiconductor) compatible wafer-scale technologies on high quality, low cost silicon substrates. However, pure passive silicon waveguide devices still have limited performance in terms of insertion loss, phase noise (which results in channel crosstalk) and temperature dependency. This is due to the high refractive index contrast between the SiO2 (silicon dioxide) cladding and the Si (silicon) core, the non-uniform Si layer thickness and the large thermo-optic effect of silicon.
Silicon nitride-based passive devices offer superior performance. Propagation loss below 0.1 dB/cm has been demonstrated for waveguides with a 640 nm thick SiNx (silicon nitride) core and even below 0.1 dB/m for waveguides with a 50 nm thick core. Also, the slightly lower refractive index contrast between SiNx (n=2) and SiO2 (n=1.45) versus Si (n=3.5) and SiO2 (n=1.45) results in less phase noise and larger fabrication tolerances. This facilitates the fabrication of high performance but still very compact optical circuits such as AWGs (Arrayed Waveguide Gratings), ring resonators, etc. Silicon nitride waveguides have been reported both as a high performance passive waveguide layer on an active silicon photonics chip but also as ‘stand-alone’ passive optical chips. Due to their compact size, these circuits are ideal for the realization of low-cost receivers and transceivers. For these applications, however, either high speed detectors, or lasers and modulators are required. Lasers cannot be fabricated in the silicon platform whilst none are possible on the silicon nitride platform.
There are two solutions for this problem. Classically active devices made using InP/GaAs materials are flip-chipped or coupled to the passive waveguide circuit. This significantly increases the complexity of the chip, as externally coupled devices require active alignment. Alternatively, one can choose to bond a III-V film 111 to the passive waveguide circuit 120 to integrate the active devices 110 on the chip to obtain an integrated optical device 100 as shown in FIG. 1. The passive waveguide circuit 120 includes a hybrid waveguide structure 125 within a SOI (Silicon On Insulator) waveguide 121 and a tapered mode converter 123. The active device 110 includes a III-V diode with quantum wells 111 attached on a SOI circuit 113 and covered by metal contacts on silicon dioxide 115. The complexity of this integration stays approximately the same whether few or many components are integrated, as the processing of all the devices is done at wafer scale. This approach therefore becomes more and more effective as the chip complexity grows.
In most heterogeneously integrated active devices, adiabatic tapering is used to transfer light between the passive circuit and the active device. This taper is fabricated in the same epitaxial layers used to create the active devices. FIG. 2 shows a photograph depicting an exemplary adiabatic taper 200 in a III-V active device. In integrated detectors, the additional length in the taper increases the capacitance, reducing the possible device bandwidth. In integrated lasers, these tapers need to be pumped in order to avoid losses. However, in this case, the injected current flows near the etched sidewalls, thereby reducing the device lifespan. In integrated modulators, the residual absorption in the taper section cannot be avoided.
The main problems with the adiabatic taper as it is used so far are excess loss due to doping, increased device capacitance and need for pumping the tapers. Excess loss is related to doping and active region, especially for the modulator. Increased device capacitance can be resolved in the modulator by electrically insulating the taper sections from the main modulating section, however this approach is not possible in the detector. Need for pumping the tapers in integrated lasers is in order to avoid excessive losses. This probably reduces the lifespan of the laser. In monolithic III-V waveguide platforms, passive and active sections are made by selectively growing active waveguide sections (with MQW, Multiple Quantum Wells and doping), and passive waveguide sections (without MQW and doping).
FIG. 3 is a schematic 300 showing typical differences between active 301 and passive 311 regions for monolithic III-V waveguide platforms. The active region 301 includes a lower layer 307 of n-InP, a middle MQW layer 305 and an upper layer 303 of p-InP attached on a common n+-InP substrate 310. The passive region 311 includes a lower layer 317 of non-doped InP, a middle layer 315 of passive material, also called quaternary layer and an upper layer 313 of non-doped InP attached on the common n+-InP substrate 310.
However, using current heterogeneous integration techniques it is not possible to use a regrown III-V wafer. This is because the III-V material is bonded to the target wafer ‘face-down’ as shown in FIG. 4 illustrating the production process 400. The unprocessed III-V die 401 is attached 402 on top of the SOI photonic waveguide 403 by “face-down” bonding 404 providing a SOI waveguide with bonded III-V die 405. Note that the “face-down” bonding 404 of the III-V die 401 inverts the epi layers. Then, substrate is removed 406 and the thin film device 407 is ready for further processing. The uneven surface topology at the interface between passive and active areas prevents successful bonding using a regrown III-V wafer, i.e. applying “face-up” bonding.
There is a need to couple light between active devices and passive waveguide circuits, in particular by using high performance, low loss adiabatic tapers between III-V active devices heterogeneously bonded to a separate wafer containing passive waveguide structures.